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Signal Integrity and Power Integrity Engineer, Pixel Watches
Signal Integrity and Power Integrity Engineer, Pixel Watches-October 2024
Mountain View
Oct 17, 2026
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About Signal Integrity and Power Integrity Engineer, Pixel Watches

Minimum qualifications:

Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

Experience with EDA tools such as Ansys HFSS, Q3D, SIwave, Cadence PowerSI, PowerDC, Allegro, APD, CST Microwave Studio, Keysight ADS, and Synopsys Hspice.

Experience with SIPI analysis, including frequency domain and time domain modeling, simulation, and correlation.

Preferred qualifications:

Master's degree in Electrical Engineering, or a related field.

Experience working in a technical environment.

Experience with advanced instruments, including VNA, TDR, Spectrum analyzer, and high-bandwidth Oscilloscope, etc.

Experience working in a lab environment, and knowledge of lab measurement and basic lab equipment.

Experience with PCB layout tools and familiarity with constraints manager.

Scripting ability for lab measurement automation or EDA simulation automation.

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Signal Integrity and Power Integrity (SIPI) Engineer, you will be responsible for the SIPI analysis and design of next-generation Pixel watches. You will be involved in each stage of the product development from the prototype to the mass production including PCB/FPCB stackup, design rules, pre-layout and post-layout simulations for electrical interfaces, critical signals, and power delivery networks (PDNs). You will closely work with cross-functional teams to solve any SIPI related design issues and provide solutions.

Simulation and measurement correlation is the key to maintaining the simulation confidence level in product development. In this role, you will be responsible for the correlation between simulation and lab measurement including the characteristics of passive channels, interface timing and PDN impedances, which require you to be familiar with lab equipment including VNA, TDR, and Oscilloscope, etc.

Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices Services team is making people's lives better through technology.

The US base salary range for this full-time position is $102,000-$150,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Participate in all stages of Pixel watch development. Own Signal Integrity (SI) and Power Integrity (PI) of Pixel watches and their subsystems.

Provide detailed SI and PI analyses report and sign-off for each design release of the product you own, including interface timing, compliance, eye mask, reflection, IO driving strength optimization etc. for signals, and DCR and PDN check to meet given power rail SPECs.

Own PCB layout constraint manager file and provide SIPI PCB layout rules for critical signal nets and power nets. Drive solutions of SIPI issues with stakeholders with cross-functional teams.

Provide simulation and simulation Design of Experiment (DOEs) to support cross-functional teams and system teams on issue debugging, root cause, solution finding, and solution optimization.

Perform correlation study between simulation and lab measurement to confirm simulation accuracy.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

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