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DFT Engineer
DFT Engineer-March 2024
Tel Aviv-Yafo
Mar 28, 2026
ABOUT AMAZON
Our mission is to be the world’s most customer-centric company.
10,000+ employees
Technology
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About DFT Engineer

  Description

  AnnapurnaLabs, as part of Amazon Web Services, is looking for talented engineers to help us develop the semiconductor platform which is based on revolutionary architecture.

  Take part in the development of cutting edge products within disruptive system architecture. You’ll have the opportunity to work on the technologies that power the world’s largest Cloud provider, within a dynamic, open, and fast-paced environment.

  AWS provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, that powers hundreds of thousands of businesses around the world.

  We are looking for Senior DFT to join the DFT design team and help develop the next generation of chips based on a revolutionary architecture. At Amazon, DFT (Design-for-Testability) is a multifaceted job that involves architecture definition, logic design, verification, test patterns generation, chip bring-up and more.

  As Senior DFT engineer, you will impact and see the device through its entire lifecycle, from definition stage to mass production. You will work in close collaboration with multiple VLSI engineering groups including chip design, verification, backend, test, reliability and more.

  To learn more about Annapurna Labs, you're welcome to watch the following videos from the recent re:Invent conference:

  AWS re:Invent 2020 - Infrastructure keynote with Peter DeSantis - https://www.youtube.com/watch?v=AaYNwOh90Pg

  AWS re:Invent 2020: Deep dive on AWS Graviton2 processor-powered EC2 instances - https://www.youtube.com/watch?v=NLysl0QvqXU

  We are open to hiring candidates to work out of one of the following locations:

  Tel Aviv, ISR

  Basic Qualifications

  • Bachelor’s degree in Computer Engineering/Electrical Engineering

  • 4+ years of experience in a semiconductor company as a DFT engineer

  Preferred Qualifications

  • Chip design, Verilog and System Verilog

  • Verification, UVM methodology

  • ATPG tools

  • Scan insertion tools

  • Gate-level simulations

  • Static timing analysis

  • Scripting (Perl/Tcl)

  • Familiarity with ATE Interpersonal Skills:

  • Energetic, self-motivated

  • Pro-active, oriented on execution

  • Attentive to details and quality

  • Team player

  • Good communications and reporting skills • Ability to work well with overseas partners

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