Job Description
Defines electrical validation strategy for IO interfaces to achieve optimized analog performance and meet product production goals. Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction. Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of IO and mixed signal architectures inclusive of industry standard datacom applications, custom Intel interfaces, and RF systems implementations. Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation. Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure. Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability. Performs debug to identify root causes and resolves all functional and triage failures for electrical issues. Tests interactions between various electrical design features using validation infrastructure. Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon validation teams to ensure capability to validate and test IO architecture implementations. Prepares validation specifications, evaluates IP, and generates test reports. Ensures products conform to standards and specifications.
Qualifications
BE/ME/MTech/MS with 10 to12 years of Electrical Validation and Lab management experience.10+ years of experienceProficient in characterizing Core analog blocks (LDOs, PLLs, BG, Term ResComp, Monitor/Observe Internal Ana/Dig signals) is a must.Proficiency in characterizing high speed protocols like PCIe, USB, DisplayPort, HDMI, SATA, UCIe, DDR is a must.Should be an expert in both compliance closure and bench debug of complex analog/msip Ips.Handling validation with Oscilloscopes, BERTs, and other EV test equipment.Should be able to prepare (in conjunction with Design Architects) and execute detailed validation test plans.Should be able to write or guide junior engineers to create Python or C/C++ scripts which help enable validation.Being proficient in Intel lab management flows and safety norms is a must.Experience creating lab capacity planning methodologies that improve validation efficiencyInside this Business Group
Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
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Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.