Job Description

　　Join Intel-and build a better tomorrow. Intel is in the midst of an exciting transformation, with a vision to create and extend computing technology to connect and enrich the lives of every person on Earth. So join us-and help us create the next generation of technologies that will shape the future for decades to come.

　　To support Intel IDM 2.0 and Foundry strategy, Technology and Design Enablement Quality and Reliability team is looking for talents to join this exciting journey to drive design enablement in quality and reliability area on Intel leading technology nodes to build industry competitive design platform supporting both internal design and external designs with IFS. The general reliability design enablement includes PDK (Process Design Kits), TFM (tool/flow/methodology), Technology, and Foundational IP (library, memory, analog IP) and DFR (Design for Reliability) development to achieve best PPA (Power Performance Area) and reliability co-optimization.

　　This role will be responsible for but not limited to:

　　Development and program management of reliability related PDK contents including all reliability mechanism and domain, QA (quality assurance) and impact analysis.

　　Drive industry EDA (Electronic Design Automation) tool and flow enablement and synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM with ease of use (EoU) features.

　　Competitive analysis and definition in technology reliability domain, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.

　　The Candidate Should Exhibit the Following Behavioral Traits:

　　Excellent written and verbal communication and presentation skills.

　　Demonstrated experience working with and or managing teams using and converting technical data into presentations.

　　Passion for quality and attention for details and procedures.

　　Demonstrated capability to drive quality enhancements projects.

　　Strong team player with proven ability to work in diverse multi-cultural environment.

　　Ability to work effectively within a global team spanning multiple countries and cultures.

　　Strong leadership capabilities building, motivating, coaching, and directing cross-functional teams and team members to meet project objectives.

　　Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment.

　　This position is eligible for Intel immigration sponsorship.

　　Qualifications

　　The successful candidate must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

　　Minimum Qualifications:

　　Bachelor's degree in electrical engineering, physics or a related field.

　　3+ years’ experience in one of the following areas: PDK development, program management, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.

　　Candidate will have a minimum of 4+ years work experience and a Bachelors degree, OR 3+ years experience and a Masters degree, OR a PhD degree.

　　Preferred Qualifications:

　　Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.

　　Experience on PDK development and validation; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM.

　　Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off; design impact and risk assessment in related reliability area.

　　Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).

　　Experiences and skills in program management, stakeholder management, and strong communication skills.

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Other Locations

　　US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.