Job Description

　　Come join the fast-paced and ever innovative area of Test Chip manufacturing and validation under the Design Engineering Group at Intel! We work on the latest IPs and process nodes across Intel’s portfolio.

　　As a Product Development Engineer - Testchip Post-Si execution your responsibilities will include but not limited to:

　　Driving and developing testability and manufacturability of analog and/or RF integrated circuits from the component feasibility stage through production ramp.

　　Contributing to design, development, and validation of testability circuits through evaluation, development, and debug of complex test methods.

　　Developing and debugging complex software programs to convert design validation flows and drive complex test equipment, including the development of digital signal processing, BERTS/Scopes, and automatic test equipment (ATE) for testing analog performance.

　　Collaborating with designers to drive design for test (DFT) features enabling efficient production testing of new products and requirements for design validation (DV) to ensure performance to internal and industry specifications.

　　Working with the design and/or product development team to perform ATEtoDV correlation, debug functionality and performance issues, perform circuit characterization, and design spec validation.

　　Evaluating new analog IP designs on ATE and works with the design, DFx, and product development teams to debug functionality and performance issues to root cause.

　　Performing ATE and bench device characterization, utilizes that data to define datasheet specifications, and performs margin2spec analysis to project yield and PHI concerns.

　　Releasing efficient production test solutions that ensure product quality and performance.

　　Engaging with manufacturing to monitor and optimize production yield and resolves any postrelease concerns.

　　Testing and characterizing for power and thermals, including thermal profiling and recipe tuning for production thermal control.

　　Providing tailored trimming and calibration for power delivery and/or thermal sensing circuits to each individual die and provides building blocks for power and performance binning and improvement.

　　Reviewing test plans with design, conversion of pre silicon content to patterns, and additional content development as needed, reviews HVM data with design to identify and root cause the issues.

　　Qualifications

　　Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

　　Minimum Qualifications:

　　Bachelor's degree in electrical engineering or any STEM related degree with at least 4 years of applicable experience in SOC analog/logic validation and characterization or a master's degree in electrical engineering or any STEM related degree and at least 3 years of applicable experience

　　3+ years of microprocessor test (ATE and/or system test and/or pre-silicon verification) experience

　　3+ years of applicable experience in analog/logic/array/functional validation in post-Si/MFG (and/or pre-Si)

　　3+ year experience in DFT/DFD, hardware testing methods and tools

　　3+ year experience with hardware language (Verilog/SV) and scripting language (Perl/Python)

　　Preferred Qualifications:

　　3+ years of experience/knowledge in

　　Circuit design/Si process/test domains

　　Memory BIST (MBIST), SSA memory architecture, LSA memory architecture, Array Redundancy, and Cache Repair

　　Scan architecture, Stuck-At scan, At-Speed scan

　　Background in ATE, automated test equipment

　　Background in test program and content development tools/methods/flows

　　Inside this Business Group

　　Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $123,419.00-$185,123.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.