Job Description

　　This position is for an Inline Defect Metrology Engineer within Oregon Assembly Test Development Factory (OATDF) Yield organization.

　　Responsibilities include but not limited to:

　　Understand the baseline defect performance, defect modes, and causes of variation within the process.

　　Take ownership of defect accuracy, spec, RFCs and working with modules on RFC response.

　　Establish and drive defect improvement roadmaps.

　　Partner with defect metrology tool owners and ADC model owners to optimize scan recipes, and ADC (Auto defect classification).

　　Collaborate with fab, die-prep, wafer-level assembly and packaging assembly group to improve inline defects and responses.

　　Define and establish yield BKMs, system and tools.

　　Create and apply concepts for optimizing component production relative to both quality and cost constraints.

　　Transfer process technologies developed in TD to VF sites in timely manner to ensure entire VF sites to run the process.

　　The candidate should also exhibit the following behavioral traits and/or skills:

　　Willingness to multitask with tolerance of ambiguity.

　　Written and verbal communication skills.

　　Technical problem-solving skills.

　　Self-motivated and self-directed work.

　　Qualifications

　　For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship Information (https://www.intel.com/content/www/us/en/jobs/hiring.html) .

　　You must possess the below requirements to be initially considered for this position.

　　Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.

　　Knowledge and/or experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

　　Minimum Qualifications:

　　Candidate must possess a Bachelor's degree with 4+ years of experience, Master's degree with 3+ years of experience or PhD degree in a science or engineering field.

　　Experience needs to be post graduate related to Engineering field.

　　Preferred qualifications:

　　1+ years of experience in one or more of the following:

　　Design of Experiments (DOE).

　　Python or other programming/scripting experience.

　　FAB Integration or Yield Experiences

　　Strong data analysis skills, able to construct clear data-based problem statements

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.