Job Description

　　Performs functional logic verification of an integrated SoC to ensure design will meet specifications.

　　Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

　　Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

　　Replicates, root causes, and debugs issues in the presilicon environment.

　　Finds and implements corrective measures to resolve failing tests.

　　Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

　　Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

　　Maintains and improves existing functional verification infrastructure and methodology.

　　Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.

　　Qualifications

　　Possess at least a degree in Electronics Engineering, Computer Engineering, Computer Science, or equivalent and experience with IP/SoC design or verification development.

　　Bachelors with at least 7 years' experience OR

　　Masters with at least 5 years' experience OR

　　Doctorate with at least 3 years' experience.

　　Strong technical leader who communicates well with great influencing skills.

　　Strong analysis, debugging skills, and creative in problem solving.

　　Motivated, Self-driven and Independent

　　Someone who wants to make a difference through technology while having FUN.

　　Additional Qualifications (EVEN BETTER):

　　Experience in any of these design tools and methodologies:- System Verilog (OVM/UVM)- Scripting (Python/Perl/Shell)- Experience in PCI Express, USBX, USB4 or any standard HSSIO protocol would be added value- RTL simulators- Interactive debugger- RTL model build- Testbench development- Power-aware simulation- Coverage-based random constraint simulation.

　　Experience in any of these areas:- Power Management- Design For Test/Verification (DFT/DFV/DFX)- Any industry standard device OR interface protocol.

　　Inside this Business Group

　　In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.