Job Description

　　Do Something Wonderful!

　　Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

　　Who We Are

　　Join the client component debug team! We debug circuit, design, and process problems in Intel's state of the art client processors. Most of the work is done on high-speed testers supplemented by laser probing equipment to look at the microscopic circuits on silicon.

　　Who You Are

　　Component Debug Engineer focused on post-Silicon product design enabling and optimization. If you like solving challenging puzzles and deep diving into new domains - this position is for you. You will be part of Intel's center of excellence for Silicon design debug supporting many product segments ranging from server to client to mobile. This team resolves product quality and performance issues blocking products from meeting production requirements with a combination of design and manufacturing problem solving expertise, leveraging state of the art methodologies and tools. Component debug is a critical ingredient to Intel's strategy of enabling strong design debug support for our entire product portfolio and scaling it going forward.

　　Qualifications

　　You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

　　Minimum Qualifications:

　　Candidate must possess a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years' experience -OR- a Master's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years' experience.

　　Experience should be concentrated in the following areas:

　　DFT (Design for Test)

　　CMOS circuit knowledge

　　Digital circuit design

　　Preferred Qualifications:

　　Experience in Silicon debug

　　Digital circuit design methodology

　　Design structural and functional diagnosis tools and methods

　　Scan and Array infrastructure

　　Scan and Array insertion with Mentor/Synopsys tools

　　Scan and Array Pre/Post Si validation, Si enabling and testing

　　Design structural and functional diagnosis tools and methods

　　Experience with post silicon validation concepts/methods including: High Volume Manufacturing (HVM), test flows including die level/package level testing, test stimulus and coverage approaches

　　Inside this Business Group

　　Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

　　Other Locations

　　US, TX, Austin; US, CA, Folsom; US, CA, Santa Clara

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $105,797.00-$175,105.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.