Description

　　A Kforce client is seeking to hire a Senior or Principal FPGA Engineer in Chandler, AZ.Summary:We are working directly with the Hiring Manager on this exclusive search assignment. The company offers a competitive compensation package including base salary, annual bonus and Stock/RSU's. A Senior or Principal FPGA Developer will be responsible for the design and development of custom medical device equipment. You will work on multidisciplinary project teams during initial feasibility, design and development, design transfer, and post release maintenance. This position is partial remote.Responsibilities Include: Analysis, design, simulation, quick prototype, and debug of electrical circuits and complex embedded systems Programming within FPGA's Senior or Principal FPGA Engineers performs laboratory measurements, analyzes data, generates conclusions about system performance to specifications and requirements Solicits, analyzes, and documents engineering requirements Maintains and update the requirements and design documentation throughout the entire system life cycle Performs requirements traceability to ensure proper allocation of system requirements to subsystems Senior or Principal FPGA Engineers creates and performs test cases, protocols, reports for unit integration, and system testing Be involved with compliance with quality system procedures and all regulatory requirements Already have existing IP Code but will be building and maintaining on the existing code

　　Requirements

　　Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or similar field; MS degree is a plus 5-8+ years of Engineering experience with programming FPGAs with Verilog and/or VHDL Experience in reading and understanding datasheets and schematics Consistently demonstrates technical proficiency and developing innovative solutions FPGA Development Tools (Altera Quartus, Xilinx Vivado) or similar Familiar with FLASH, RAM, Cache would be ideal Quartus development tool experience or similar would be ideal Familiar with any of the following PLL, DDS, ADC Experience Reading schematics and understand electronics is preferred Experience in FPGA IP Core usage and timing closure is preferred Understanding of IQ demodulation, FIR implementations with coefficient development, notch filters, and the ability to generate FPGA code to implement the routines is a plus Familiar with SPI, I2C, UART, Ethernet protocols is a plus

　　The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

　　We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

　　Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.

　　This job is not eligible for bonuses, incentives or commissions.

　　Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.