Job Family: Research Development

Req ID: 423449

We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us – whichever path you take, we’re looking forward to seeing your point of view!

We make real what matters!

About the Role

The person would be responsible for improving SW quality of the Questa Simulation product line. The role would involve working very closely with RD teams to improve the quality of the code by using aspects of correct by construction methodology.

Requirement:

Knowledge of HDLs (Verilog, system verilog, VHDL and system C) Knowledge of methodology like UVM, Assertion, Coverage and Power aware/estimation Knowledge of Simulation platform is desirable Good communication skills. Knowledge of at least one scripting language (sed/awk/shell/perl) Knowledge of software debug processes is a plus ASIC design / Verification experience is an added advantage Working knowledge of C/C++ Knowledge of Jira/Confluence tracking tool is desirable A never say die attitude, challenging oneself to always get better is what we are looking for Has worked on Simulation, validation or verification projects

Qualifications:

B.Tech/M.Tech from a reputed institute Has worked on Simulation, validation or verification projects

We are Siemens.

A collection of over 379,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!

We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home.