At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

　　Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

　　At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Job Title: Principal Verification Engineer (SERDES)

　　Location: Cork

　　Reports to: Group Director

　　Job Overview:

　　The Principal Verification Engineer will take a Technical Leadership role on the Verification team (Digital & AMS) as part of a SERDES Product Team located at Cork, Ireland.

　　Job Responsibilities:

　　Verification of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS)Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet)Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking and ClosurePrototyping, Emulation, Customer delivery and supportWork with cross-functional teams ranging from architecture, all aspects of circuit design, Layout development, RTL design & Validation, Physical design & Test chip development Participate in technical leadership of the team in the areas of digital design and verification, SERDES architecturesWork with global teams (US, west coast and east coast), which work in different time-zones

　　Job Qualifications:

　　Candidate's background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and developmentWorking knowledge of a set of common SERDES standardsWide experience with digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVMExperience of Assertion Based Formal Verification essentialExperience of Front-end design tools covering LINT, Synthesis & CDC AnalysisExcellent problem-solving skills and ability to work cooperatively in a team environmentExcellent communication and stakeholder management skillsBEng, MEng or PhD

　　Additional Skills/Preferences:

　　Prior experience with post Silicon validation & customer IP deployment of one or more Serial IO IPs/ complex Memory Interface IPs is an added advantageKnowledge of PCIe, CXL protocols preferred

　　Additional Information:

　　Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

　　Travel: >10%

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