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Principal Firmware Engineer
Principal Firmware Engineer-February 2024
Austin
Feb 10, 2026
About Principal Firmware Engineer

  Microsoft Silicon and Cloud Hardware Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. CHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Skype, OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for Principal Firmware Engineer to help achieve that mission.

  As Microsoft's cloud business continues to grow the ability to deploy new offerings and Hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Firmware Center of Excellence (Firmware CoE) as part of SCHIE organization is instrumental in defining and delivering operational measures of success for software/firmware stack for Microsoft Azure, improving the quality, delivery, scale and sustainability related to Microsoft Cloud hardware. We are looking for dedicated engineers with a passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

  The Firmware CoE is responsible for hardware/firmware for Azure Infrastructure. We are working on the next generation hardware/firmware for server, GP-Graphic Processing Units (GPUs), silicon and rack infrastructure with a focus on innovation in firmware technology to secure Azure infrastructure for Microsoft and their customers.

  We are looking for a highly dedicated Principal Firmware Engineer with a background in Unified Extensible Firmware Interface (UEFI), firmware architecture, and design to work on lighting up these various technologies as each team produces their part.

  Responsibilities

  Demonstrate the capability of leading firmware development through product development cycles for new and sustaining products.

  Experience with UEFI architecture, x86 or ARM firmware flows, Remote Access Server (RAS) design flows, and system bring up activities.

  Demonstrate knack for root causing issues at the intersection of multiple subsystems across firmware and hardware.

  Coaching team members and helping them grow.

  Embody ourCulture (https://careers.microsoft.com/v2/global/en/culture) & Values (https://www.microsoft.com/en-us/about/corporate-values)

  Qualifications

  Required Qualifications:

  Bachelor's Degree in Computer Science, or related technical discipline AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python

  OR equivalent experience.

  6+ years of professional experience in designing, developing Embedded Software and Firmware solutions in UEFI, Tiano Core EDKII, C & Assembly, resulting in solving complex hardware/firmware interface issues.

  Experience working with Arm SoC firmware ecosystem and how it intercepts with UEFI stack from early concept of SoC Architecture and design to shipping final product.

  Experience working with cross divisional teams on hardware debug and root cause analysis.

  Other Requirement:

  Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

  Preferred Qualifications:

  The successful candidate should have experience with some or all the following: Trusted Firmware-Arm (TF-A), UEFI, Standalone-MM, PCIe, memory interfaces, RAS, Operating System (OS) primitives, memory management, scheduling, interrupts, threading.

  Experience with Implementation of Hardware/Firmware Security and firmware enablement primitives.

  Experience in CPU Server Architectures such as Intel, AMD & ARM is preferred.

  Experience with Platform initialization, Board support package integration, low level drivers for peripherals such as PCIe, I2C, eMMC, SPI, USB, UARTs as well as Memory Management, Scheduling, Interrupts and multi-threading.

  Experience with Architecting, Designing and Delivering on new Data Center class technologies across the entire platform.

  Software Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.

  Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

  #azurehwjobs

  Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .

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