Job Description

　　Intel’s Xe IP Engineering drive to best-in-class Graphics, Media and Display IP requires expert implementations of a vast range of numerical algorithms. The quality of our numerical hardware IP is determined by architecture, micro-architecture, algorithm, number format selection, precision, accuracy, RTL implementation, gate level optimization and ultimately physical placement. At each step of the process the capacity for orders of magnitude change to final power, performance and area is reduced.

　　The Graphics Numerical Hardware & System Level Design group works on all aspects of numerical hardware design from machine readable specifications, algorithm design, modelling in various languages including C++, RTL creation and optimization with formal verification applied through-out. The group works on high level synthesis and system level design in general. The group operates as an applied research group and internal consultancy working with and enabling the various teams architecture, micro-architecture, modelling, design, verification and validation. As an applied research group everything we do is novel and used in production, we academically & industrially publish, patent and change execution. We create and use research tools in house to improve all aspects of hardware design, we super use existing EDA tools, collaborate with vendor R&D to improve those tools and drive vendors to productize entirely new features.

　　NSD is built on four pillars: consultancy (product facing engagements), tools (in house, vendor, hybrid), verticals (domain specific tool chain for particular numerical hardware applications) and our research program (collaborations with key academics and we fund PhD students who are members of the group at the same time as conducting directly relevant PhD research).

　　NSD was founded on the premise that deep mathematical and logical reasoning, and research in general can deliver significant hardware benefits in terms of reliability, speed, area, power efficiency and execution. As an internal consultancy we work to extract the true necessary requirements, phrase the right design problem, explore the design space and fully formally prove the correctness of experimental designs. Quality means that challenging legacy decisions comes with the territory, innovation and insight are prized and every bit matters.

　　The Opportunity:

　　We are seeking a highly skilled High-Level Synthesis (HLS) Engineer to join our dynamic team. The ideal candidate will have a strong background in digital design, software design and a deep understanding of high-level synthesis tools and methodologies. In this role, you will be responsible for developing and implementing high-level synthesis strategies to optimize hardware design and performance.

　　Key Responsibilities:

　　Develop and optimize digital designs using high-level synthesis tools. Convert complex algorithms and data structures from high-level programming languages into efficient hardware implementations. Analyze and optimize hardware designs for performance, area, and power consumption. Implement strategies to meet stringent performance and power efficiency targets. Work closely with cross-functional teams, including software engineers, hardware engineers, and system architects, to ensure seamless integration of high-level synthesis designs. Provide technical leadership and mentorship to junior team members. Continuously evaluate and integrate new high-level synthesis tools and methodologies to improve design flows and outcomes. Develop custom tools and scripts to automate and streamline the HLS process. Address complex design challenges with innovative solutions. Keep abreast of the latest advancements in high-level synthesis and apply them to solve real-world design problems. Ensure that all designs meet industry standards and specifications. Conduct thorough testing and validation to guarantee the reliability and functionality of hardware designs.

　　Behavioral skills we are looking for:

　　Excellent problem-solving, analytical, and communication skills

　　Ability to work collaboratively in a team environment and lead technical discussions

　　Qualifications

　　This is an entry level position and will be compensated accordingly. You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research and relevant previous job and/or internship experience.

　　Minimum Qualifications:

　　Bachelor's Degree in Electrical or Electronic Engineering, Computer Engineering or related STEM degree and 3+ years of experience in the following:

　　Proven experience in high-level synthesis, digital design, or hardware implementation.

　　Strong expertise in programming in C++.

　　Preferred Qualifications:

　　Master's Degree in Electrical or Electronic Engineering, Computer Engineering or related STEM degree.

　　Familiarity with digital design tools and methodologies, including ASIC design flows.

　　Experience with SystemC programming

　　Experience with SystemVerilog

　　Experience with Cadence Stratus

　　Knowledge of scripting languages such as Python or Tcl for design automation.

　　Experience in optimizing designs for low power consumption and high performance.

　　Inside this Business Group

　　The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.