Job Description

　　This position is within the Design Enablement (DE) organization of Technology Development(TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable design teams to get to market faster with leadership products on cutting-edge technologies.

　　As part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and

　　drive PDKs towards industry-standard methods and ease of use for the end customers.

　　The job requires partnering and leveraging domain experts across various areas of Technology Development, EDA vendors and product design teams to develop and deliver high-quality technology collaterals, models, and enablement of EDA tools.

　　The Design Technology Enablement Engineer plays a key role by bringing together the experts to drive enablement of technology features for PDKs in the domains of Device modeling, LVS, Parasitic Extraction, and Reliability/Physical Verification.

　　Responsibilities are but not limited to:

　　Define technical specifications for Intel advance technology features to enable Intel-specific and industry-standard EDA design tools.

　　Coordinate development of these technology features, develop QA plans and drive test-cases development working with relevant stakeholders.

　　Engage with internal partners and external EDA vendors to coordinate tool feature requirements and specifications.

　　Joint effort with partners in DE organization and external DTCO to evaluate and isolate performance contributors for technology features as part of enablement.

　　Build and qualify Process Pathfinding Kits and tools with quick turnaround time.

　　Drive innovation and initiatives to enhance existing automation, tools and methodology.

　　Identify and analyze problems, plans, tasks and solutions.

　　Cultivate and reinforce appropriate group values, norms and behaviors.

　　Perform in a dynamic, challenging and sometimes ambiguous environment with drive and creativity.

　　The candidate should also exhibit the following behavioral traits and/or skills:

　　Creative, independent, and out-of-the-box thinker with problem-solving skills and analytical ability.

　　Attention to details and organization skills.

　　Depth and breadth of being able to connect the dots and identify cross-discipline optimal solutions.

　　Self-motivated, leadership skills being able to influence across the internal and external ecosystems.

　　Written and verbal communication skills to present complex issues with clarity to drive decisions.

　　Soft skills to work with cross-functional and cross-site teams and influence multiple internal and external stakeholders.

　　Work in a dynamic and team-oriented environment.

　　This is an entry level position and compensation will be given accordingly.

　　#DesignEnablement

　　Qualifications

　　You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

　　Minimum qualifications:

　　Candidate must possess a MS degree with 6+ months of experience or PhD degree with 1+ year of experience in Electrical Engineering or Computer Engineering or related field.

　　6+ months experience in the following:

　　LVS, Parasitic Extraction, Device Modeling and Simulation tools/flows.

　　Custom design flow and related EDA tools.

　　CMOS device physics, process technology and design rules.

　　Preferred Qualification:

　　6+ months experience in the following:

　　Tools, flows, and methodology for optimal Product Performance/Power/Area/Cost (PPA).

　　One of the following: Python, PERL, TCL

　　Familiar with Reliability verification, ESD concepts, Standard Cell Library and Memory Architectures.

　　Physical verification runsets development.

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Other Locations

　　US, AZ, Phoenix; US, CA, Santa Clara

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $106,231.00-$159,109.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will require an on-site presence.