Job Description

　　Do Something Wonderful!

　　Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

　　Who You Are

　　The Component Debug Engineer evaluates and resolves component engineering design and physical design issues. Ensures products have necessary design for debug features to enable deep silicon isolation capabilities. Utilizes system setups, testing equipment, automated systems, and lab probe/FIB/prep tools to isolate microscopic silicon circuits while under test. Performs fault isolation to root cause silicon failures, isolate defect modes, and engages with crossfunctional teams such as test and validation engineers, circuit designers, wafer fabrication process engineers, and high volume manufacturing for efficient and accelerated failure analysis. Partners to resolve any quality issues, sharing ownership of failure analysis, temporary mitigation options, and permanent remedies. Provides inputs on investigation areas for failure analysis or design process improvement and ensure performance to specifications. Develops new debug technologies, methodologies, and tools to advance the state of the art for silicon debug.

　　Qualifications

　　You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

　　Minimum Qualifications:

　　Candidate must possess a bachelor's degree in electrical engineering, Computer Engineering, or a related field with 6+ years' experience -OR- a master's degree in electrical engineering, Computer Engineering, or a related field with 4+ years' experience.

　　Preferred Qualifications:

　　Experience in Silicon debug

　　DFT (Design for Test)

　　Digital circuit design methodology

　　Design structural and functional diagnosis tools and methods

　　Scan and Array infrastructure

　　Scan and Array insertion with Mentor/Synopsys tools

　　Scan and Array Pre/Post Si validation, Si enabling and testing

　　Design structural and functional diagnosis tools and methods

　　Post silicon validation concepts/methods including:

　　High Volume Manufacturing (HVM)

　　Test flows including die level and package level testing

　　Test stimulus and coverage approaches

　　Inside this Business Group

　　Manufacturing and Product Engineering (MPE) is responsible for test development across product segments, supporting 95% of Intel's revenue. We deliver comprehensive pre-production test suites and component/physical debug capabilities to enable high quality, high volume manufacturing.

　　Other Locations

　　US, CA, Santa Clara; US, MA, Hudson

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $105,797.00-$175,105.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.