We are now looking for a ASIC Design Engineer - Hardware. As a member of our ASIC backend/timing team, you'll be working on product designs, focusing on such tasks as clocks, timing convergence, chip layout planning, design optimization and automation of work flows. Specifically you'll be focusing on full chip layout planning (partitioning, planning clock distribution and other structures, methodology), full chip timing closure signoff (using tools such as Synopsys Primetime, Cadence Tempus etc.), design optimization, and gate-level design of high-speed logic. In this role you will also interface with architecture, rtl design, layout implementation, methodology and custom design teams to drive design implementation, timing analysis/closure all the way from micro-architecture to tape-out.

　　What you'll be doing:

　　Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.

　　Chip level Integration, physically partitioning and floor planning.

　　Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc.

　　Design optimization and timing convergence related tasks.

　　Development of PD work flows.

　　What we need to see:

　　BS or MS in Electrical Engineering or Computer Science, or equivalent experience.

　　3+ years of relevant ASIC design experience ideally with a focus in timing.

　　Good problem-solving skills and ability to work with cross functional teams solving tough physical design problems is essential.

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