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Senior Pre-Si Validation Engineer
Senior Pre-Si Validation Engineer-July 2024
Virtual
Jul 15, 2025
ABOUT INTEL
Intel creates world-changing technology that enriches the lives of every person on earth.
10,000+ employees
Technology
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About Senior Pre-Si Validation Engineer

  Job Description

  CEG HIP MYS is seeking experienced IP RTL validation engineers to join our talented and vibrant team. You will be directly involved in delivering next-generation LPDDR5/DDR5 PHY RTL verification for SOC application on Intel leading process node.

  Key Responsibilities include but not limited to:

  Owning RTL Validation for Functional and/or DFx

  Creating OVM/UVM based TB as a platform for RTL validation

  Developing BFM to interface with the IP with the capability of monitoring transaction and checking protocol.

  Defining verification strategies, methodology and writing detail test plan for each feature owned to ensure effective RTL validation.

  Coordinate cross functional efforts with Design and Architecture teams to achieve full coverage verification plan.

  Developing testcases, assertions and functional coverage using System Verilog based on the test plan.

  Setting up and running GLS to verify the async and multi-cycle paths.

  Debugging any test failures in RTL and GLS, finding and implementing corrective measures for the failing tests

  Analyzing functional coverage, code coverage and LPC to identify and close all gap to achieve full coverage.

  Developing automated tools or scripts for the pre-silicon validation environment to improve efficiency

  Collaborating with SS/SOC on IP integration and resolving all integration issues.

  Qualifications

  Preferred Qualification:

  Experienced in IP validation through multiple full project cycles to gather in-depth experience in validation skillsets and design knowledge

  Fluent in System Verilog, OVM/UVM and verification methodologies

  Experience/knowledge in DDR is strong advantage

  Experience in using standard industry verification tools such VCS, DVE, Verdi, etc.

  Good understanding of RTL, UPF, logic design knowledge and DFx

  Tcl/Tk/Perl/Python to automate verification flow and improve efficiency

  Familiar with UNIX, and well-versed in Shell and C Programming

  Strong in problem solving, debugging various simulation failures, formal verification etc.

  Strong written and oral communication skill. Able to communicate well with counterparts and key stakeholders including cross-site partners.

  Posting Statement

  All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

  Benefits

  We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

  Working Model

  This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

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