Job Description

　　You will be part of Intel's Programmable Solution Group PSG, working on complex ASIC and FPGA designs in leading edge process nodes.

　　Responsibilities entail, but not limited to:

　　Design and integration of complex high speed protocol IP's which requires in-depth knowledge of memory technologies specifically related to DDR protocol solutions, work with pre-silicon and post-silicon teams in validating protocol compliance

　　Tasks include authoring detailed functional architecture/microarchitecture specification, developing surrounding logic, integration and optimization of any memories and hard macros required, writing timing constraints

　　RTL and constraint quality checks including Lint, CDC, Fishtail, LEC

　　Contribute to chip-level integration: interface definition, clock/reset architecture, RTL, timing constraints integration

　　Development, assessment, and refinement of RTL design to target power, performance, area and timing goals

　　Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis

　　Support IP, subsystem, and full-chip level verification by providing design requirements, review verification plan, functional/code coverage results, and simulation debug

　　Power state definition and management dynamic clocking solutions, clock generation and asynchronous clock crossing strategies

　　Work with Chip Architecture, Design Verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs

　　Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process

　　Qualifications

　　Minimum Qualifications :

　　The successful candidate's minimum qualifications will include the following:

　　BS in electrical engineering or computer science with 12+ years of experience

　　6+ years of experience in high performance digital logic design, HW/SW Co-design and integration

　　6+ years of experience with synthesis, static timing analysis

　　5+ years of experience developing tools/flows to improve efficiency of RTL Design execution

　　3+ years of experience with Perl/TCL/Python

　　Inside this Business Group

　　The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $186,760.00-$299,166.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

　　Position of Trust

　　This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.