Summary:

　　Meta is looking for an experienced Silicon Packaging Engineer for its Ecosystem and Technical Operation team. The ideal candidate will be able to operate in a highly multi-tasked, fast-paced and very cross-functional engineering environment. They will have experience with hardware development and integration of machine learning clusters, both server and fabric. They will be very familiar with AI/HPC hardware development, and will be data-driven and focused on the impact they can create as part of a world-class engineering team.The Meta Infrastructure team designs, builds, brings-up, tests and integrates hardware systems that power Meta’s platforms, deployed in data centers worldwide, from silicon to sheet metal. Designs are published through the Open Compute Project Foundation.This is a rare opportunity to join our team and help us build some of the world’s most open and efficient machine learning platforms.We are building a competency in packaging design and technology to support the development of custom silicons for Infrastructure hardware as well as to develop packaging solutions that are optimal for our AI/ML products and system level performance.

　　Required Skills:

　　Silicon Packaging Engineer Responsibilities:

　　Development of advanced packaging technologies( SMT, solder ball attach, and other assembly process) roadmap for AI/ML and networking products applications.

　　Drive ecosystem partners for 2.5D/3D and large packages SMT roadmap.

　　Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging, design feasibility studies and analyses to ensure good manufacturing at ODM.

　　Participates early on Si/package/PCB/system co-design, and ODM SMT manufacturing work in product development design reviews providing feedback on manufacturability and helps incorporate latest technology advancements and design rules.

　　Work with internal Si, architecture and system teams and externally engaged partners, ODM, design houses and OSAT companies.

　　Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package form factor for next generation versions of current products.

　　Create, conduct, and analyze Design of Experiments (DOE) for development and sustaining activities.

　　Work cross-functionally with design, NPI, quality and reliability, manufacturing teams and support new technology integration into products.

　　Support selection, and qualification of external partners (ODM, OEM, OSAT).

　　Drafting of SMT assembly and advanced packaging technology definition documentation.

　　Understand PCB and SMT assembly process details, FMEAs, and Quality metrics.

　　Collaborate with internal and external stakeholders to ensure seamless integration of packaging technology into product development cycles.

　　Stay abreast of the latest advancements in advanced packaging technologies and market trends.

　　Identify and evaluate emerging technologies with potential for future applications.

　　Ability to travel internationally, typically once per quarter.

　　Minimum Qualifications:

　　Minimum Qualifications:

　　BS in Materials Science, Mechanical Engineering or equivalent industry experience

　　7+ years of experience in advanced packaging with surface mount technology and assembly process development and manufacturing

　　In-depth knowledge of flip chip, 2.5D and 3D packaging technologies

　　Experience taking products from concept to production including development of manufacturing specifications, vendor qualifications and improvement of manufacturing efficiencies and costs

　　Effective communication skills

　　Experience working effectively with cross-functional teams

　　Preferred Qualifications:

　　Preferred Qualifications:

　　Masters Degree or PhD in Materials Science, Mechanical Engineering, or other related disciplines

　　10+ years of experience in advanced packaging assembly process, SMT

　　In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps

　　Proven understanding of surface mount technology (SMT) and its application in advanced packaging

　　Experience working with ODM, assembly packaging, OSAT, and foundry partners

　　Proven technical understanding of full range of semiconductor packaging materials, material interactions, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques

　　Familiarity or experience with Finite Element Modeling (FEM) of thermal and thermo-mechanical behavior of packages

　　Proven knowledge of packaging industry standards (IPC, JEDEC, IEEE, ISO, ANSI)

　　Understanding of package qualification and reliability methods and failure analysis

　　Public Compensation:

　　$170,000/year to $240,000/year + bonus + equity + benefits

　　Industry: Internet

　　Equal Opportunity:

　　Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

　　Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].