The Microsoft Silicon Engineering and Solutions Team is looking to hire a Senior Silicon Engineer to join our Central Front-End Tools, Flows and Methodology (TFM ) group.

　　This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas likeRegister Transfer Level (RTL) & Verification Intellectual Property ( VIP Design) , Design Verification, Validation, Design for testing (DFT), Emulation, Design Synthesis, RTL Power Anaysis, Physical Design ( PD) Handoff and System on Chip (SoC) integration. This team supports numerous simultaneous projects within Microsoft by developing workflows and software for our design engineers so that they can deliver cutting-edge silicon solutions for Microsoft.

　　Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

　　Responsibilities

　　Be part of a central Front End Computer Aided Design (FE CAD) team that drives common FE methodologies for SoC and Intellectual Property (IP) design.

　　Be the go-to-lead in your domain and act in partnership with the execution team.

　　Provide leadership to the design community for the Computer Aided Design ( CAD) domain for which you are responsible.

　　Work with stakeholders across the Microsoft Silicon group to collect TFM requirements.

　　Develop, enhance, and integrate common design and verification IP for organization-wide use. 

　　Work with Electronic Design Automation ( EDA) vendors to adopt the most optimal solutions for silicon verification and design.

　　Mentor other team members and summer interns.

　　Other

　　Embody our Culture (https://www.microsoft.com/en-us/about/corporate-values) and Values (https://careers.microsoft.com/us/en/culture)Qualifications

　　Required/Minimum Qualifications

　　7+ years of related technical engineering experience

　　OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

　　OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

　　OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

　　7+ years of experience in digital design or CAD flows/tools development in this area.

　　4 + years of expereince in Design Synthesis

　　2+ years of demonstrated expereince in one of the following areas:

　　Design compile, elaboration and filelist/libraries handling.

　　Design release packaging and qualification, RTL quality flows, static checks.

　　Low Power design.

　　Other Requirements

　　Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

　　Addtional or Preferred Qualifications

　　MS in Electrical Engineering, Computer Engineering, Computer Science

　　OR equivalent work experience.

　　10+ years of relevant experience.

　　Demonstrated expereince in CPU/SoC design principles.

　　Experience with Logic Design compilation, elaboration and synthesis flows

　　Experienced writing scripts/software with industry standard languages like Python, TCL, Perl, C/C++ or Java (Python preferred)

　　Experience using industry standardHardware Description Languages( HDLs) like SystemVerilog/Verilog. 

　　In-depth knowledge of Front-End workflows, methodologies, and best practices. 

　　Ability to design and verify reusable design components.

　　Experience in Synthesis and Timing Constraints. Exposure to tools T, Fishtail, Formality/ Logic Equivalence Checking (LEC), Genus, Fusion Compile.

　　Demonstrated expereince in RTL power/Unified Power Format (UPF) linting flows like Power Artist/Jules, Verification Checks Low Power (VCLP).

　　Experience in RTL filelist generation, SoC connectivity, integration.

　　Hands on experience with RTL 2 Physical Design( PD) handoff process.

　　Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year.Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

　　Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .