We are looking for a Senior Physical Design Engineer . As part of our DPU silicon team in Santa Clara, you will help lead the way for our cutting-edge ASICs, supporting world-class silicon Physical Design.

　　Responsibilities

　　Tackle complex Physical Design challenges in critical parts of our designs.

　　Provide leadership on critical issues like timing signoff and flow validation/improvement.

　　Help with flow automation.

　　Work closely with Physical Design team and design teams to solve complex issues.

　　Qualifications

　　Required/Minimum Qualifications:

　　7+ years of related technical engineering experienceo OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

　　o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience

　　o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

　　7+ years of physical design experience, including hands-on experience in place & route, and STA.

　　4+ years of experience with Synopsys implementation/signoff tools (such as ICC2/Fusion-Compiler and PrimeTime).

　　2+ years of experience on scripting (TCL/Perl) and/or flow automation.

　　Other requirements:

　　Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.Preferred Qualifications:

　　10+ years of physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR).

　　Experience with flow automation/validation and QOR improvement.

　　Solid scripting skills in Perl or TCL.

　　Detailed understanding of STA & timing constraints.

　　Tapeout experience in TSMC 7nm or below, or comparable.

　　Experience implementing complex serdes interfaces like PCIE and/or Ethernet.

　　Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $112,000 - $218,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $145,800 - $238,600 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

　　Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

　　#azurehwjobs #HIFE

　　Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .