Job Description

　　Drives and leads the entire full-chip integration activities including floorplanning/design-planning, partitioning, pin-cutting, PG grid generation, PDN/ESD closure, RDL/analog routing, bump-planning, LV cleanup, tapeIN flows and final gds delivery. Full responsible for defining the physical dimensions of the IP or SoC with consideration for overall product costs such as die size optimization, die-per-reticle/good-die-per-wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Establishes the integration plans for disaggregated die with optimization for package and board constraints. Performs integration of all dies in a package and completes the relevant checks before tapeout. Creates and physical database for the IP or SoC. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect-ratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power. Acts as a PoC between the Integration team and all the other internal/external stakeholders. Drives all the signoff/quality reviews, waivers coding/approvals, documentations and the entire TI activity for gds delivery.

　　Qualifications

　　Minimum Qualifications:

　　Bachelor or Masters degree in Electrical/Electronics/Computer Engineering with 9+ years of relevant experience

　　Expertise in full-chip floorplanning, design planning for multiple style of floorplans including partitioning and pin-cutting for large SoCs and good knowledge of related areas like bump-planning, rdl routing, analog, full chip-integration activity

　　Exposure to LV cleanup, power-planning, ESD, PG grid generation

　　Experience as a technical lead driving any FC Integration activity

　　Preferred Qualifications:

　　Proficiency in using multi vendor EDA tools including ICC2, FC, or other SNPS/CDNS tools etc

　　PKG and platform knowhow/exposure, SORT/CLASS test awareness is a definite plus

　　PnR flow experience/Timing analysis knowhow, physical aware synthesis awareness

　　Proficiency in programming language /scripting(Perl, tcl, Python) is a plus

　　Inside this Business Group

　　The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.