Job Description

　　This position is within the Design Enablement(DE) organization of Technology Development(TD). At Intel, Design Enablement is one of the key pillars enabling Intel to deliver winning products in the marketplace. The PERC ESD development team within this organization is looking for individuals who will be responsible to develop PERC ESD rule decks for latest Intel technologies. Your work will directly enable design teams to get to market faster with leadership products on cutting edge technologies. AS part of the Design Enablement/Process Design Kit (PDK) group, you will join a highly motivated team of top-notch engineers solving challenging technical problems enabling PDKs for Intel's most advanced process technologies and drive PDKs towards industry standard methods and ease of use for the end customers.

　　#DesignEnablement

　　Qualifications

　　You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

　　Minimum Qualifications:

　　Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering or Computer Engineering or related field.

　　3+ years of experience in the following:

　　Experience with Calibre or ICV or Pegasus PERC tools.

　　ESD/ L atch-up Pre-Si models

　　Preferred Qualifications:

　　3+ years of experience in the following:

　　(HBM and CDM), I/O design and methodologies.

　　Debugging skills.

　　Experience in writing physical verification runsets.

　　Experience in extraction and physical design domain.

　　Experience in scripting languages for QA automation.

　　Experience in driving cross functional and industry wide initiatives and taskforces.

　　*Knowledge of semiconductor device physics, process technology, and design rules.

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Other Locations

　　US, TX, Austin; US, AZ, Phoenix; US, CA, Santa Clara

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $144,501.00-$217,311.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.