Job Description

　　About the Group:

　　As an integral part of Intel's new IDM2.0 strategy, we are establishing Intel Foundry Services IFS, a fully vertical, standalone foundry business, reporting directly to the CEO. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can choose from including x86 cores, graphics, media, display, AI, interconnect, fabric, and other critical foundational IP, along with Arm and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers' products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications.

　　About the Role:

　　Intel Foundry Services is looking for a Std Cell Library IP lead who has industry and/or Intel experience to:

　　Drive std cell library portfolio planning and decisions in alignment with IFS platform and targeted market segments

　　Hands on experience in standard cell design techniques and architectural tradeoffs

　　Ability to evaluate cell architectures, design and optimize for best-in-class cell PPA for custom cell development.

　　Ability to contribute technically as well as lead a team of individual contributors.

　　Institute robust IP QA (quality assurance) audits and practices to ensure high quality library deliveries to IFS customers.

　　Drive technical discussion with IFS customers and 3rd party IP supplier engagements.

　　In-depth knowledge in digital design including CMOS combinatorial logic and sequential circuit and layout.

　　Strong understanding of Std cell modeling, extraction, and characterization highly desired.

　　Experience in EDA tool/flow/methodology for cell characterization, EDA view generation (timing, noise, power, etc.) and validation is a must.

　　This individual will socialize and drive decisions with IFS stakeholders by synthesizing std cell requirements from customers, gather market intelligence and work with internal and 3rd party IP suppliers to develop a rich platform portfolio on leading-edge foundry technologies to enable customer products and address market segments with best-in-class PPAC (power, performance, area, cost) libraries.

　　The selected candidate for the std cell library lead position will be responsible for but not limited to:

　　Ability to synthesize customer std cell requirements into specifications that are best in class for PPAC.

　　Hands on experience with detailed cell architectures and specifications to drive custom std cell development.

　　Demonstrate deep technical knowledge of std cell library development based on past or present experience.

　　Demonstrate the ability to collaborate, influence and drive decisions in a cross-functional setting.

　　Partner with IFS ecosystem team as a subject matter expert to facilitate std cell library development through 3rd party IP suppliers.

　　The ideal candidate should exhibit the following behavioral traits:

　　Service mindset with a focus on quality solutions, drive velocity of execution and thrive in solving complex problems for customers and suppliers.

　　Skills with ecosystem partnership collaborations.

　　Qualifications

　　You must possess the below minimum qualifications to considered for this position. Preferred qualifications are in addition to the minimum requirements and will be a factor in identifying top candidates.

　　Minimum Qualifications:

　　MS degree with at least 15+ years additional experience, or a PhD with 3+ years additional experience, in Electrical Engineering or Physics, or related field with

　　Minimum 7+ years' experience in designing std cell libraries on leading edge technologies with silicon validated IPs in high volume products.

　　Minimum 7+ years' experience in technical problem solving.

　　Demonstrated E2E std cell library design - spec definition, architecture feasibility, cell circuit and layout designed with industry standard EDA tools and flows, library characterization, pre- and post-Si validation, collateral QA, and delivery.

　　Understanding technology and design tradeoffs for std cell development is a must.

　　Familiarity with EDA tool suite used for cell design, development and signoff, cell characterization and EDA view generation and validation, and customer collateral readiness.

　　Preferred qualifications:

　　Highly proficient in std cell design techniques and trade-offs

　　Ability to be customer focused and obsessed in driving technical engagements and meeting std cell library delivery milestones with high quality collaterals.

　　Bring external foundry best practices to drive custom std cell development and enable characterization kits a big plus.

　　Experience working with multiple foundry technologies is a plus.

　　In-depth knowledge /experience with Intel technology is a strong plus.

　　Excellent project and program management skills to mitigate risk and drive execution to meet customer schedule commitments.

　　Strong communication and presentation skills to executive management

　　Inside this Business Group

　　Intel Foundry Services (IFS) is an independent foundry business that is established to meet our customers' unique product needs. With the first "Open System Foundry" model in the world, our combined offerings of wafer fabrication, advanced process, and packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities help our customers build their innovative silicon designs and deliver full end-to-end customizable products from Intel's secure, resilient and sustainable source of supply.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

　　Position of Trust

　　This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.