At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

　　Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

　　At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

　　Job Title: Digital Layout Design Engineer II (SERDES)

　　Locations: Cork, Galway, Dublin

　　Reports to: Group Director

　　Job Overview:

　　The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious physical design engineers (PD) who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm).

　　The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).

　　The Digital Layout Design Engineer (II) will take a role on the PCS digital layout design team.

　　Job Responsibilities:

　　Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure while working in collaboration with digital circuit designersOptimize and maintain the central RTL2GDS implementation/signoff flow which will be used by the global PD teamThe candidate will have the opportunity to work on many varieties of challenging designs, e.g. low power and high-speed design. The responsibility includes participating in or leading next-generation PHY IP physical design, methodology, and flow developmentThe Candidate will work on the PPA target evaluation and co-work with the design and constraint team to improve the design, constraint, and brainstorm how to raise the PPA bar of next-generation PHY IPThe Candidate will work on the new process physical implementation flow development such as TSMCN3Co-work with other functional teams (Design/STA/Analog/Package/Verification) to optimize the high-speed PHY IP development flow and define IP signoff criteriaWork on the PHY IP physical implementation guide used for our customers and internal global PD teamsWork with Technical Team Leads in the areas of PCS digital layout design and PHY top levelsWork with global teams (US, west coast and east coast), which work in different time-zones

　　Job Qualifications:

　　BEng, MEng or PhDCandidate's background should include a minimum of 2 years of experience in CMOS SERDES or high-speed I/O IC layout design and developmentAssist with the architecting and implementation of complete PHY gds with integration of PMA, PCS hierarchies and optimized clock and power distribution strategiesExperience with ASIC design flow, hierarchical physical design strategies, and methodologies and understanding deep sub-micron technology issues expected.Good scripting skills and flow/CAD support experience desirableWorking knowledge with some of LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM an advantage.Automation and programming-minded, coding experience in Tcl/Perl/Python desirableGood physical implementation flow debugging skillsDesire understanding RTLWorking with layout designers from groups all over the world to build high quality IP and test chipsWorking with circuit designers and project managers from groups all over the world to understand their technical and schedule needsInnovative, self-motivated, excellent problem-solving skills, design aptitude, good communication skills and ability to work cooperatively in a team environment

　　Additional Skills/Preferences:

　　Cadence tool experience and design experience at >10Gbps and in < 40nm technologiesCollaborating with the Cadence R&D teams (Virtuoso, PVS developers) to help develop the layout editing and verification tools and flows

　　Additional Information:

　　Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

　　Travel: >10%

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