Reference #: R018418Please Note:1. If you are a first time user, please create your candidatelogin account before you apply for a job. (Click Sign In > Create Account)2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:

　　The candidate should be able work independently on both top level floor planning and assembly, and block level and IP level layout of analog and high speed digital design. In addition to layout, the candidate must be able to coordinate with the circuit designers and other members of the layout team. The candidate will need to be able to work with both analog design engineers, analog layout engineers, place and digital designers in the review critical aspects of the layout work.

　　The candidate should be able to understand how to implement design requests including power/ground nets, critical device matching, parasitic minimization and sensitive signal routing. The candidate should be able to recognize how decisions at the current level of integration affects the design hierarchy above and below this level. The candidate should have a good understanding of ESD concepts including how to best use guard rings for design isolation. The candidate should be able to engage with team members leveraging others knowledge while sharing their own learning. Collaboration amongst all engineers is key for this position.

　　The candidate should have extensive experience in using Cadence Virtuoso, Calibre LVS and DRC, Synopsys StraRC or Cadence QRC extraction. Additionally, candidate should be proficient with either Ansys Totem or Cadence VoltageStorm for IR drop and EM analysis. Expertise with Unix scripting required.

　　Candidate should have minimum 12+ years of hands-on experience in Analog or RF layout. Experience with analog modules such as SerDes, ADCs/DACs, and PLLs is a plus. Candidate should have in-depth understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, and experience in layout in FinFet technologies is required.Preference will be given for candidates with experience in 5nm and 3nm process nodes.

　　Education should include a Bachelor of Science degree.

　　Additional Job Description:Compensation and Benefits

　　The annual base salary range for this position is $126,000- $210,000

　　This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

　　Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

　　Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

　　If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

　　Broadcom Inc. is committed to creating a diverse work environment and is proud to be an equal opportunity employer.