Job Description

　　CEG HIP MYS is seeking senior Structural Design Engineer to join our talented and vibrant team. You will be directly involved in delivering next generation DDRPHY designs for SoC applications on Intel leading process node

　　Key Responsibilities for this position includes but not limited to:

　　Technical expertise in the RTL to GDSII phase of the ASIC design flow

　　Top level partitioning, budgeting, pin placement, IR analysis , both static and dynamic

　　Proficient in aspects of physical design from RTL handoff through streaming out a clean GDSII such as Floorplan, Synthesis, Auto Place and Route, Clock Tree Synthesis techniques and clock tree optimization, Timing analysis and optimization with ideal and propagated clock trees, Performance Verification, Reliability Verification, Power Analysis and Optimisation, Timing Closure etc.

　　Handling of floorplan iterations to conclude on the correct partitions, pin placement based flyline and connectivity between different blocks, global route based congestion estimation, power pushdown, clock tree pushdown, integration, ECO generation, top level physical verification signoff etc.

　　Exposure to industry standard EDA standard tools related to physical design such as IC compiler, fusion compiler, primetime etc.

　　Possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment.

　　Qualifications

　　You should possess a relevant educational qualification, BSEE or equivalent with 5+ years/MSEE or equivalent with 4+ years design experience in the structural/physical design domain. Additional qualifications include:

　　Have multiple tapeout experience in deep submicron

　　Experience in relevant VLSI structural/physical design methodology, flows and relevant EDA tools will be an advantage

　　Experience in Block level and Fullchip floor planning and power grid planning.

　　Previous experience as a key technical leading role in development and delivery of leading edge physical databases for ASICs, SoCs or IPs will be an advantage

　　Experienced in industry RTL to GDSII tools: Fusion Compiler, Design Compiler, IC Compiler II, PrimeTime, etc

　　Handson expertise with scripting languages such as Python, Perl, TCL, and knowledge of hardware description languages VHDL and Verilog.

　　Experience/knowledge in DDR is strong advantage

　　Familiar with UNIX, and well-versed in Shell and C Programming

　　Strong in problem solving, debugging various simulation failures, formal verification etc.

　　Strong written and oral communication skill. Able to communicate well with counterparts and key stakeholders including cross-site partners

　　Other Locations

　　MY, Kulim

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.