SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR. DSP ASIC/FPGA DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to 1.5M+ users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.The Starlink modem team is seeking motivated, proactive, and intellectually curious engineers who can work with world-class cross-disciplinary teams (firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will implement system algorithms and silicon solutions for cutting-edge communication systems for deployment in space and ground infrastructures. These systems are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.RESPONSIBILITIES:Participate in all phases of ASIC/FPGA design flow - from concept to mass productionDevelop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, and create specification documentsDevelop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)Optimize your designs for area, speed, and power to meet system requirements; analyze architectural trade-offsDevelop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checkingVerify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineersCollaborate with verification engineers to develop UVM-based top-level tests for your blocksParticipate in SoC-level and FPGA top-level integration activitiesPrototype designs on FPGA, focusing on closely emulating the final product functionalityUse scripting languages to achieve higher performance and improve productivity through automationPerform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checksRun implementation tools, such as Synopsys Design Compiler, Xilinx Vivado, and others; perform timing closure for your designsWork with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICsBring-up and validate ASICs and FPGAs in the lab, utilize various lab equipmentCollaborate with software engineers in developing production software for your designsBASIC QUALIFICATIONS:Master's degree in an engineering discipline5+ years of experience in SystemVerilog, Verilog or VHDL RTL designExperience designing DSP and/or digital communication system datapath blocksPREFERRED SKILLS AND EXPERIENCE:Experience in working with ASICs and/or FPGAsExperience in designing DSP, digital communication system datapath blocks, and/or modem designStrong programming and scripting skills in most of these languages: MATLAB, Python, C/C++, Perl, Tcl, Make, BashUnderstanding of clock domain crossing (CDC) techniquesExperience in FPGAs, evaluation boards, and knowledge of FPG