We Are:

The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.

You Are:

An experienced CAD/Automation Engineer with experience in digital ASIC design and verification and will develop IP packaging and qualification flow for internal use and external delivery.

The Work:

Scripting and automation of design database qualification and packaging

Integration of foundry libraries, including 5nm, for IP verification packaging

Creation of packaging flow of design and verification components

Checks and validation of package consistency

Propagation of packaging flow requirements with internal IP teams

Support and maintenance of qualification tools and scripts (lint, CDC, sim)

Running of stand-alone IP testbench for qualification

Initial debug of failures and issues and work w/ IP teams for resolution

Maintaining package and release timelines for various projects

Working with cross functional teams (DV/Arch/Design/FW) to ensure quality and completeness of release collateral

Here’s what you need:

A minimum of two years of experience with ASIC Design (RTL2GDS), CAD Automation and RTL Design Verification

Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

Experience with development of fully automated flows

Strong Python scripting skills

Strong Unix, Shell, Make skills

Knowledge of ASIC design flow automation, testbench integration

Knowledge of low level HW/SW interaction and debug

Experience with RTL Gate Level Simulations

Experience with power analysis methodology

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in California, Colorado, New York or Washington as set forth below.

We accept applications on an on-going basis and there is no fixed deadline to apply.

Information on benefits is here.

Role Location Annual Salary Range

California $63,200 to $220,400

Colorado $63,200 to $190,400

New York $58,500 to $220,400

Washington $67,300 to $202,700

#LI-NA

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Candidates who are currently employed by a client of Accenture or an affiliated Accenture business may not be eligible for consideration.

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