Description

　　The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Lab’s Chip development team.

　　The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.

　　The team’s work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGA’s substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

　　Key job responsibilities

　　As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration at the Die level, through SI/PI simulation and package layout, to reference board design aspects.

　　The scope of your work will include:

　　• Deep dive into electrical IPs, integrated into the DIE;

　　• I/O ring design and close work with Backend team on floor-planning all I/O interfaces at the DIE level.

　　• Lead test studies of Die bump-out arrangements and Package substrate breakout.

　　• Lead layout test studies of package pin-out arrangements and PCB board breakout.

　　• Design large and complex package substrates.

　　• Carry advanced SI/PI extractions and simulations to validate the design from the silicon to the peer device at the board level.

　　This position is for an experienced engineer with strong background in high-speed electrical interfaces, such as DRAM, PCIe, Ethernet SerDeses. The line of work is multi-disciplinary, combining Package-Design, Back-End integration of electrical IPs, SI/PI extractions & simulations.

　　We are open to hiring candidates to work out of one of the following locations:

　　Haifa, ISR

　　Basic Qualifications

　　• BSc in Electrical Engineering.

　　• Experience in Layout (PCB or Package), or BackEnd integration of electrical IPs.

　　• Familiarity with Signal and Power integrity simulation tools.

　　• Strong passion to learn and gain deep understanding.

　　Preferred Qualifications

　　• Knowledge of Chip, Package and PCB co-design methodology.

　　• Knowledge in high-speed digital interfaces such as DRAM/PCIe/SerDes.

　　• Knowledge in power-integrity and power-delivery of low-voltage high-current – an advantage

　　• Hands on experience with lab testing and characterization – an advantage.

　　• Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice) - an advantage