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Senior Verification Engineer

Senior Verification Engineer-March 2024

Bangalore

Mar 28, 2026

About Senior Verification Engineer

　　Responsibilities :

　　• Testbench development using System Verilog and UVM

　　• UVM components development.

　　• Create Verification plans required for the project.

　　• SV coverage constructs, SV Assertions

　　• Knowledge of C/C++ is very much added advantage

　　• Leveraging existing test benches, methodologies and industry best known practices

　　• Handle block/Module/IP level verification independently.

　　• Create various verification components in SystemVerilog and using related methodology guidelines

　　• Debug issues and present / discuss problems with designers independently

　　• Proactive attitude required in understanding and debugging.

　　• Run regression, analysis reports, achieve code coverage and functional coverage goals

　　• Run netlist verification without and with SDF

　　• Python or perl or any other scripting knowledge is advantage.

　　Share your resume to [email protected]

　　#LI-VS1

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