Introduction

Your role and responsibilities

design and development of Instruction

Sequencing Unit for high-performance Processor CPU of IBM Systems.

Architect and design Instruction Dispatch to Issue queues, RegisterRenaming for Out of Order Execution, Issue instructions to Execution

Pipelines, Reordering Buffers for completion of a high performance

processor CPU

Develop the features, present the proposed architecture in the High leveldesign discussions

Estimate the overall effort to develop the feature.

Estimate silicon area and wire usage for the feature.

Develop micro-architecture, Design RTL, Collaborate with other Core

units, Verification, DFT, Physical design, Timing, FW, SW teams to develop

the feature

Signoff the Pre-silicon Design that meets all the functional, area andtiming goals

Participate in post silicon lab bring-up and validation of the hardware

Lead a team of engineers, guide and mentor team members, represent

aDesign and development of Instruction

Sequencing Unit for high-performance Processor CPU of IBM Systems.

Architect and design Instruction Dispatch to Issue queues, RegisterRenaming for Out of Order Execution, Issue instructions to Execution

Pipelines, Reordering Buffers for completion of a high performance

processor CPU

Develop the features, present the proposed architecture in the High leveldesign discussions

Estimate the overall effort to develop the feature.

Estimate silicon area and wire usage for the feature.

Develop micro-architecture, Design RTL, Collaborate with other Core

units, Verification, DFT, Physical design, Timing, FW, SW teams to develop

the feature

Signoff the Pre-silicon Design that meets all the functional, area andtiming goals

Participate in post silicon lab bring-up and validation of the hardware

Lead a team of engineers, guide and mentor team members, represent

as Logic Design Lead in global forums.

Required technical and professional expertise

2 - 5 years of demonstrated experience in architecting and

designing Instruction Dispatch unit of CPU

Hands of experience of implementing Issue Queues, Register renamingand forwarding, Reordering Buffer and Pipeline flush/exception handling

Deep expertise in Out of Order, Super Scalar, Multi-Threaded CoreArchitecture and ISA

Experience with high frequency, instruction pipeline designs

At least 1 generation of Processor Core silicon bring up experience

In depth understanding of industry microprocessor designs (e.g., x86,

ARM, or RISC-V processor designs)

Proficiency of RTL design with Verilog or VHDL

Nice to haves

Knowledge of Instruction Decode and Execution units

Knowledge of verification principles and coverage

High-level knowledge of Linux operating system

Knowledge of one object oriented language and scripting

language

Understanding of Agile development processes

Experience with DevOps design methodologies and tools.

Preferred technical and professional experience

Hiring manager and Recruiter should collaborate to create the relevant verbiage.