Job Family: Research Development

Req ID: 420640

Mentor Graphics a part of Siemens EDA, is looking for a research and development engineer who is required to understand, design and implement algorithm-centric solutions in the high-level synthesis. The role is for industry leading high level synthesis tool – Catapult-C which takes ANSI C /C++ (https://en.wikipedia.org/wiki/C%2B%2B)  and SystemC (https://en.wikipedia.org/wiki/SystemC%22%20/o%20%22SystemC)  inputs and generates register transfer level  (RTL) code targeted to FPGAs  and ASICs .

Catapult–C tool is used by top hardware design companies for designing cutting edge semiconductor chip design in automotive/machine learning/wireless design/video and image processing etc.

We are looking for a collaborator to help us improving our IP catalog. The ideal candidate will focus on the Qofr quality of the IPs delivered with Catapult tool.

As part of the core synthesis team; you will:

help our IP designer to design optimal IPs.

identify the optimizations required to achieve best Qofr.

contribute to the implementation of those optimizations.

These are exciting times in our space - we are growing fast and working on ambitious new initiatives. 

https://eda.sw.siemens.com/en-US/ic/ic-design/high-level-synthesis-and-verification-platform/

Required Education, and Experience

Master’s degree or PhD graduates in EDA or related areas with degree and proven experience in Computer Science or equivalent.

The Ideal Candidate should demonstrate:

Technical Skills (Must have):

Strong programming knowledge in C/C++ and object-oriented design skills.

Excellent algorithm and data-structure design skills with theoretical and practical experience in implementation of complex algorithms.

Script-programming skills with languages such as TCL, Perl, Python, Shell, etc.

Familiarity with Unix/Linux operating systems.

Strong analytical and problem-solving capabilities.

Technical Skills (Desirable) : In few of the below areas

Understanding/Prior experience in design / implementation of EDA algorithms in the areas of logic synthesis and optimization / High level synthesis / Timing analysis / Formal verification

Experience in hardware modelling in VHDL/Verilog/SystemC

Understanding of digital design for ASIC or FPGA.

Hardware architecture and trade offs for digital arithmetic design.

System level hardware modelling in areas of Virtual prototyping / Hardware-software co-design etc.

Prior experience in working/designing of complex algorithms and optimization

Experience in Compiler design – Language parsing/ Abstract syntax tree optimization/transformation / Loop optimizations / Parallel compiler /Software pipelining / Register allocation etc

General Skills: Strong positive attitude, Good presentation and communication skills, Self-driven and self-motivating, Able to implement technical solutions independently, Relationship building capabilities, Team player.