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CPU Design Manager, Google Cloud
CPU Design Manager, Google Cloud-June 2024
Bangalore
Jun 16, 2026
ABOUT GOOGLE
Our mission is to organize the world’s information and make it universally accessible and useful.
10,000+ employees
Technology
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About CPU Design Manager, Google Cloud

  Qualifications minimales:

  Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent practical experience.

  20 years of experience in logic/RTL design.

  Experience with modern processor microarchitecture and related technologies/algorithms, microarchitecture definition and RTL design.

  Experience with modern high-frequency CPU design implementation results, front-end design, low power Implementations, power analysis tools for CPU, and ARM Instruction Set Architecture.

  Qualifications souhaitées:

  Master’s degree or PhD in Electrical Engineering or Computer Science.

  Experience leading a team for part of a processor front-end design, for ARM based modern processors.

  Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

  In this role, you will contribute in all phases of complex designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality RTL. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.

  Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

  Lead a team of engineers in the Bangalore Core IP design organization working on IP Design and Integration.

  Develop CPU front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.

  Propose performance enhancing microarchitecture features, and work with Architects and Performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements.

  Deliver designs meeting PPA goals with production quality. Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance modeling effort.

  Work with the Functional Verification team to ensure production of quality designs, and the physical design team to meet frequency, power, and area goals.

  Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.

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