Google welcomes people with disabilities.

　　Minimum qualifications:

　　Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.

　　5 years of experience in physical design.

　　Experience with PnR/APR, STA, EMIR, and DRC tools/flows working on synthesized designs.

　　Experience in one or more scripting languages (e.g., Tcl, Python, etc.).

　　Preferred qualifications:

　　Experience with low-power design techniques such as multiple power domains, power switches, level shifting, isolation, and dynamic voltage/frequency scaling using Unified Power Format (UPF).

　　Experience with advanced Engineering Change Order (ECO) techniques including full layer and metal-only changes.

　　Experience with synthesis and optimization methodologies.

　　Experience with Analog and Mixed Signal (AMS/DMS) design integration including custom routing, shielding, and analog macro integration.

　　Experience working with scaled Complementary Metal Oxide Semiconductor (CMOS) processes (e.g., FinFET).

　　Knowledge of version control systems such as Git.

　　Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

　　Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

　　Generate high quality PnR/APR results for one or more digital blocks, including DRC and LVS signoff, working closely with front end designers and back end physical design integration engineers.

　　Close timing on blocks using modern STA tools and techniques while suggesting improvements to the design when issues arise.

　　Analyze power integrity (EMIR) of blocks and implement fixes once issues are identified.

　　Optimize designs based on key metrics, including power, area, and performance trade-off analyses.

　　Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.

　　Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.