Minimum qualifications:

　　Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.

　　8 years of experience with low power verification and flows.

　　Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at subsystem or full-chip level.

　　Experience in C/C++ or SystemVerilog based tests and test sequence development.

　　Preferred qualifications: Master's degree in Electrical Engineering or Computer Science.

　　Experience with low power coverage closure and power aware simulations.

　　Experience with debugging power aware simulations issues during bring-up and verification cycle.

　　Knowledge of UPF from the user perspective and low power design strategies and power managers in subsystem or full-chip.

　　About the job

　　Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

　　Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

　　Responsibilities

　　Be part of a team to verify complex digital design blocks at Subsystem level or Full Chip level by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi core based C tests using reusable C test libs. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.