Job Description

　　Hands-on experience with layouts of critical memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array, decoders, etc., in compiler context. Hands-on experience with top-level memory integration and DRC, LVS, density and other physical verification checks across the compiler space. Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electro migration, voltage drop (IR), ESD, and other reliability checks on the layouts. Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files), performs area impact assessment with updated PDKs. Performs detailed physical array planning, power planning, area optimization, critical wire analysis, custom leaf cell layout. Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests. Knowledge of and experience with advanced FinFET processes in 5nm, 3nm.Able to bridge gap b/n circuit designers and layout designers. Independently drive layout execution, plan tasks, track them to completion to achieve high quality deliverables on time.

　　Qualifications

　　Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:5+ years experience with Cadence Virtuoso Layout Editor tool knowledge.

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.