Job Description

　　About the Technology Development and Design Enablement Groups:

　　Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs) and foundational IPs (FIPs), and carries out technology lead vehicle execution for Si validation. Enablement and optimization of EDA reference flow and design flow on Intel technology play a crucial role in accomplishing DE's charter.

　　About the Role:

　　The TD/DE EDA Design Flow Development Manager will build a team of CAD experts and developers and will be responsible for planning, execution, delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff. This is a highly technical leadership position that requires strong expertise and experience in EDA tool/flow development, SoC design methodology, analog and mixed signal design methodology and execution. The position requires strong project management skills as well as business influencing skills with our external EDA partners to drive optimization of EDA flow on Intel technology. The candidate must be results-oriented, capable of driving disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes.

　　Experience Required:

　　Deep working knowledge of all aspects of SoC design in a product setting - floor planning, RTL design, circuit simulation, logic synthesis, place and route, clock tree construction, extraction and timing signoff, signal integrity analysis, layout and reliability verification, and full chip integration.

　　Demonstrated experience in establishing and qualifying SoC design flow and/or AMS design flow from an EDA reference flow and addressing product specific design/methodology requirements and design database management.

　　Demonstrated experience in successful EDA team leadership and project management. Proven leadership and management skills: cross functional team cooperation, employee development, problem solving, conflict resolution and project management.

　　Demonstrated ability to understand and interpret industry EDA trend in response to advanced node requirements, drive design flow initiatives to align.

　　Proficiency with one more major (EDA) software platforms (Synopsys, Cadence, Siemens).

　　Excellent written and verbal communication skills.

　　Qualifications

　　MS or PhD degree in electrical engineering, computer engineering or similar field.

　　10+ years of experience in the development of EDA tools and flows.

　　Inside this Business Group

　　As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

　　Other Locations

　　US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

　　Posting Statement

　　All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

　　Benefits

　　We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

　　Annual Salary Range for jobs which could be performed in US, California: $186,760.00-$299,166.00

　　*Salary range dependent on a number of factors including location and experience

　　Working Model

　　This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.

　　Position of Trust

　　This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.