Summary:

　　Meta Reality Lab is the world leader in the design of virtual and augmented reality systems. Come work alongside expert engineers and research scientists to create the technology that makes VR pervasive and universal. Join the adventure of a lifetime as we make science fiction real and change the world. The Display Architecture Team within the VR organization is seeking a Display Algorithm Architect to lead the development of Meta’s proprietary display IP for VR displays. As a member of the VR Display Team, the successful candidate will be working closely with Display Driver IC (DDIC) and pixel pipeline engineers, Visual Quality team, and DDIC vendors to design, evaluate performance, and embed Meta’s proprietary visual quality IP within the vendor's DDIC or in SoC for future VR products. This role offers involvement in a mix of forward-looking and product-critical projects, and requires close collaboration with multiple teams within the Meta Reality Labs.

　　Required Skills:

　　Display Algorithm Architect Responsibilities:

　　Lead architecture and development of proprietary display IP for VR displays including owning the reference software model for the algorithms.

　　Collaborate with DDIC pixel pipeline architects to optimize algorithms for optimal gate-count and timing.

　　Collaborate with visual quality teams to evaluate performance.

　　Collaborate with hardware prototyping teams to create hardware evaluation and platforms.

　　Collaborate with the system and DDIC engineers to bring up and test the algorithms for production readiness.

　　Minimum Qualifications:

　　Minimum Qualifications:

　　Masters Degree in Electrical Engineering, or Computer Engineering, or equivalent work experience.

　　12+ years of industry experience including 5+ years of technical leadership working with multiple internal and external teams.

　　Prior experience with architecture and design of display IP such as sub-pixel rendering, foveation, Mura, burn-in compensation algorithms.

　　Proficient in at least one programming language such as Matlab, Python or C++.

　　Effective communication skills and a record of publications.

　　Preferred Qualifications:

　　Preferred Qualifications:

　　Ph.D. in Electrical Engineering.

　　Good understanding of the front-end digital design flow: RTL design, logic synthesis, timing verification.

　　Good understanding of pixel pipeline for Displays and DDIC architecture.

　　Experience with FPGA prototyping.

　　Familiar with compression IP design such as DSC.

　　Public Compensation:

　　$204,000/year to $281,000/year + bonus + equity + benefits

　　Industry: Internet

　　Equal Opportunity:

　　Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

　　Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].