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　　DFT Engineer

　　Broadcom's ASIC Product Division is seeking candidates for a DFT position atourFort Collins, Colorado Development Center. The successful candidate willbe responsible for leading DFT programs all the way from chip level DFTspecification, through to implementation and verification culminating insuccessfully releasing products to production.

　　The candidate would be required to work on various phases of SoC DFT relatedactivities for Broadcom APD (ASIC Products Division)'s designs - DFTArchitecture, Test insertion and verification, Pattern generation,Coverage improvement, Post silicon debug and yield improvement to meet theproduct test metrics. It involves working with the Physical Design & STAteam for DFT mode timing closure. The role could also involve directinteraction with external customers.

　　It is expected that you can code using TCL, PERL, RUBY, PYTHON,C++ or similar.Responsibilities:

　　Understanding Broadcom & customer DFT feature requirements & DPPM goals& defining appropriate DFT specifications for the ASIC

　　Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDesand other I/P DFT integration

　　Working closely with STA and DI Engineers design closure for test

　　Generating, Verifying & Debugging Test vectors before tape release.

　　Validating & Debugging Test vectors on ATE during the silicon bring up phase

　　Assisting with silicon failure analysis, diagnostics & yield improvementefforts

　　Interfacing with the customer, physical design and testengineering/manufacturing teams located globally

　　Working closely with I/P DFT engineers & other stakeholders

　　Debugging customer returned parts on the ATE

　　Innovating newer DFT solutions to solve testability problems in 7nm & beyond

　　Automating DFT & Test Vector Generation flows

　　Skills/Experience:

　　Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan,BIST, and others)

　　Scan Insertion and scan compression background (DFT Compiler, MentorTestKompress, etc.)

　　Logic BIST design and debug experience

　　Well-versed in ATPG vector generation, simulation, and debugging.(TetraMax, Fastscan)

　　Experience in Verilog coding, testbench generation & simulation

　　Memory BIST insertion and verification experience on embedded (SRAM,CAM, eDRAM, ROM)

　　Boundary scan Verification and test vector generation. Should have goodknowledge in IEEE1149.1 and IEEE1149.6

　　Basic knowledge Test-STA and constraints

　　Strang background on IEE1687, IJTAG, ICL and PDL

　　The ability to work in a multi-disciplined, cross-department environmentSolid knowledge in analog and digital circuit design, and device physicsfundamentalsGood understanding of Si processing, logical and physical synthesis, andtransistor reliability principles

　　Excellent problem solving, debug , root cause analysis and communicationskills

　　Experience working on ATE is a plus

　　Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification andsilicon debug is a plus

　　Experience working on Tessent SSN is a plus

　　Education & Experience:

　　Bachelors in Electrical/Electronic/Computer Engineering and 8+ years ofrelevant industry experience or Masters Degree inElectrical/Electronic/Computer Engineering and 6+ years of relevantindustry experience