Minimum qualifications:

　　Bachelor's degree in Electrical Engineering or equivalent practical experience

　　6 years of experience with IP Development or Integration

　　Experience in RTL development with Verilog/SystemVerilog

　　Experience with a scripting language such as Perl or Python

　　Experience in area, power, and performance optimization

　　Preferred qualifications:

　　Master's degree or PhD in Electrical Engineering or Computer Science

　　Experience implementing Camera ISP image processing blocks or other multimedia IPs such as Display or Video Codec

　　Domain knowledge in one or more of these areas: AMBA AXI, CSI/DSI/DP, image/video/display processing

　　Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step.

　　In this role, you will be responsible for RTL design development of Camera ISP designs. This includes RTL coding, Lint cleanup, SoC IP release flows, architecture, micro-architecture, PPA optimizations, test-planning collaboration, coverage reviews, and closure for high quality and optimized Camera IP deliveries.

　　Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

　　The US base salary range for this full-time position is $146,000-$220,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

　　Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

　　Provide microarchitecture definition for Camera IP hardware designs and subsystem/ASIC top-level integration that meet competitive power, performance, and area targets.

　　Perform RTL coding, function/performance simulation, debug and Lint/CDC/FV/UPF checks.

　　Participate in synthesis, timing/power closure and FPGA/silicon bring-up, and create tools/scripts to automate tasks and track progress.

　　Participate in test plan and coverage analysis of the sub-system and chip-level verification.

　　Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.

　　Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.